ARM Cortex-M3 User Manual

Bus Interface
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12.9 Unaligned accesses that cross regions
The CM3Core supports ARMv6 unaligned accesses, and performs all accesses as
single, unaligned accesses. They are converted into two or more aligned accesses by the
DCode and System bus interfaces.
Note
All Cortex-M3 external accesses are aligned.
Unaligned support is only available for load/store singles (LDR, STR). Load/store
double already supports word aligned accesses, but does not permit other unaligned
accesses, and generates a fault if this is attempted.
Unaligned accesses that cross memory map boundaries are architecturally
Unpredictable. The processor behavior is boundary dependent, as follows:
• DCode accesses wrap within the region. For example, an unaligned halfword
access to the last byte of Code space (
0x1FFFFFFF ) is converted by the DCode
interface into a byte access to
0x1FFFFFFF followed by a byte access to 0x00000000 .
• System accesses that cross into PPB space do not wrap within System space. For
example, an unaligned halfword access to the last byte of System space
(
0xDFFFFFFF ) is converted by the System interface into a byte access to 0xDFFFFFFF
followed by a byte access to 0xE0000000.
0xE0000000 is not a valid address on the
System bus.
• System accesses that cross into Code space do not wrap within System space. For
example, an unaligned halfword access to the last byte of System space
(
0xFFFFFFFF ) is converted by the System interface into a byte access to 0xFFFFFFFF
followed by a byte access to
0x00000000 . 0x00000000 is not a valid address on the
System bus.
• Unaligned accesses are not supported to PPB space, and so there are no boundary
crossing cases for PPB accesses.
Unaligned accesses that cross into the bit-band alias regions are also architecturally
Unpredictable. The processor performs the access to the bit-band alias address, but this
does not result in a bit-band operation. For example, an unaligned halfword access to
0x21FFFFFF is performed as a byte access to 0x21FFFFFF followed by a byte access to
0x22000000 (the first byte of the bit-band alias).
Unaligned loads that match against a literal comparator in the FPB are not remapped.
FPB only remaps aligned addresses.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit