ARM Cortex-M3 User Manual

Signal Descriptions
A-18 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
A.15 WIC interface
Table A-15 lists the signals of the WIC interface.
Table A-15 WIC interface signals
Name Direction Description
WA K E U P Output Active high signal to PMU that core must be made active.
WICSENSE Output Active high set of signals indicating which input lines the
WIC would generate WA K E UP signal in response to.
WICPEND Output Captured interrupt information for NVIC.
WICENACK Output Active high SLEEPDEEP is WICSLEEP
acknowledgement to PMU.
WICDSREQn Output Active low request to NVIC to make SLEEPDEEP mode
WIC-sleep.
FCLK Input Clock synchronous to NVIC FCLK input.
nRESET Input Asynchronous active low reset.
WICDISABLE Input Debugger active signal to disable WIC mode when a
debugger is attached.
WICINT Input Peripherals Active high interrupt, debug monitor, NMI, and
or RXEV signals.
WICMASK Input Active high set of signals indicating which input lines the
WIC should generate a WA K E U P signal in response to.
WICLOAD Input Load interrupt sensitivity list into WIC from NVIC
WICCLEAR Input Clear sensitivity list in WIC.
WICENREQ Input Make SLEEPDEEP mode WIC mode sleep request from
PMU.
WICDSACKn Input Active low SLEEPDEEP is WICSLEEP
acknowledgement from NVIC.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit