ARM Cortex-M3 User Manual

Trace Port Interface Unit
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 17-5
Trace out
The trace out block serializes formatted data before it goes off-chip.
Advanced Trace Bus interface
The TPIU accepts trace data from a trace source, either direct from a trace source (ETM
or ITM) or using a Trace Funnel. For more information, see Advanced Trace Bus
interface.
Advanced Peripheral Bus interface
The APB interface is the programming interface for the TPIU. For more information,
see Advanced Peripheral Bus interface.
17.1.3 TPIU inputs and outputs
This section describes the TPIU inputs and outputs. It contains the following:
• Trace out port
• Advanced Trace Bus interface on page 17-6.
• Miscellaneous configuration inputs on page 17-6
• APB interface on page 17-7.
Trace out port
Table 17-1 describes the trace out port signals.
Table 17-1 Trace out port signals
Name Type Description
TRACECLKIN Input Decoupled clock from ATB to enable easy control of the trace port speed. Typically this
is derived from a controllable clock source on chip, but an external clock generator could
drive it if a high speed pin is used. Data changes on the rising edge only.
TRESETn Input This is a reset signal for the TRACECLKIN domain. This signal is typically driven
from Power on Reset, and must be synchronized to TRACECLKIN.
TRACECLK Output TRACEDATA changes on both edges of TRACECLK.
TRACEDATA[3:0] Output Output data for clocked modes.
TRACESWO Output Output data for asynchronous modes.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit