ARM Cortex-M3 User Manual

Programmer’s Model
2-6 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Figure 2-2 Application Program Status Register bit assignments
Table 2-1 describes the bit assignments of the APSR.
Interrupt PSR
The Interrupt PSR (IPSR) contains the Interrupt Service Routine (ISR) number of the
current exception activation.
Figure 2-2 shows the bit assignments of the IPSR.
Figure 2-3 Interrupt Program Status Register bit assignments
31 30 29 28 27
N Z C V
0
ReservedQ
26
Table 2-1 Application Program Status Register bit assignments
Field Name Definition
[31] N Negative or less than flag:
1 = result negative or less than
0 = result positive or greater than.
[30] Z Zero flag:
1 = result of 0
0 = nonzero result.
[29] C Carry/borrow flag:
1 = carry or borrow
0 = no carry or borrow.
[28] V Overflow flag:
1 = overflow
0 = no overflow.
[27] Q Sticky saturation flag.
[26:0] - Reserved.
31 0
Reserved ISR NUMBER
89

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit