ARM Cortex-M3 User Manual

Nested Vectored Interrupt Controller
8-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Table 8-2 describes the bit assignments of the Interrupt Controller Type Register.
Auxiliary Control Register
Use the Auxiliary Control Register to disable certain aspects of functionality within the
processor.
The register address, access type, and Reset state are:
Address
0xE000E008
Access Read/write
Reset state
0x00000000
Figure 8-2 shows the bit assignments of the Auxiliary Control Register.
Figure 8-2 Auxiliary Control Register bit assignments
Table 8-2 Interrupt Controller Type Register bit assignments
Bits Field Function
[31:5] - Reserved.
[4:0] INTLINESNUM Total number of interrupt lines in groups of 32:
b00000 = 0...32
a
b00001 = 33...64
b00010 = 65...96
b00011 = 97...128
b00100 = 129...160
b00101 = 161...192
b00110 = 193...224
b00111 = 225...256a
a. The processor only supports between 1 and 240 external interrupts.
31
0
Reserved
12
DISFOLD
DISDEFWBUF
3
DISMCYCINT

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit