ARM Cortex-M3 User Manual

Exceptions
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-15
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5.7 Late-arriving
A late-arriving interrupt can pre-empt a previous interrupt if the first instruction of the
previous ISR has not entered the Execute stage, and the late-arriving interrupt has a
higher priority than the previous interrupt.
A late-arriving interrupt causes a new vector address fetch and ISR prefetch. State
saving is not performed for the late-arriving interrupt because it has already been
performed for the initial interrupt and so does not have to be repeated.
Figure 5-4 shows an example of late-arriving interrupts.
Figure 5-4 Late-arriving exception timing
In Figure 5-4, INTISR[8] pre-empts INTISR[2]. The state saving for INTISR[2] is
already done and is not required to be repeated. Figure 5-4 shows the latest point at
which INTISR[8] can pre-empt before the first instruction of the ISR for INTISR[2]
enters Execute stage. A higher priority interrupt after that point is managed as a
pre-emption.
CURRPRI[7:0]
HRDATAI[31:0]
INTISR[2]
INTISR[8]
INTISR[9]
HADDRS[31:0]
HWDATAS[31:0]
HADDRI[31:0]
CLK
PC r0 r1 r2 r12r3 LR
100 500 504 600 604 608
100 500 600
Fetch of
ISR6
Fetch of
ISR12
First ISR instruction
is in Execute stage
123 645 789 1210 11 13 14 15 16 1917 18 20 21 2422 23 25
ETMINSTAT[2:0]
ETMINTNUM[8:0]
000 100 000001
8-cycle ISR entry
latency
018 024 025
104 108
FF
Fetch of
ISR15
09
SP+18
SP+1C
SP+0
SP+4
SP+8
SP+C
SP+10
SP+14
xPSR0x48
0x60
0x64

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit