ARM Cortex-M3 User Manual

System Debug
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-5
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11.3 System debug programmer’s model
This section lists and describes the debug registers for all the system debug components.
It contains:
• FPB on page 11-6
• DWT on page 11-13
• ITM on page 11-30
• AHB-AP on page 11-39.
Note
• For a description of the Core debug registers, see Core debug registers on
page 10-3.
• For a description of the SWJ-DP and SW-DP registers see Chapter 13 Debug
Port.
• For a description of the TPIU, see Chapter 17 Trace Port Interface Unit.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit