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Signal Descriptions

Unrestricted Access Non-Confidential

ETMFOLD Output Opcode fold. An IT opcode has been folded in this cycle. PC advances past the

current (16-bit) opcode plus the IT instruction (16 bits). This is reflected in the

ETMIA.

ETMFIFOFULL Input Driven by the ETM (if connected). ETMFIFOFULL is asserted when the

ETM FIFO is full, and causes the processor to stall until the FIFO has drained,

so ensuring that no trace is lost.

DSYNC Output Synchronization pulse from DWT.

Table A-12 ETM interface (continued)

Name Direction Description

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ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit