ARM Cortex-M3 User Manual

Embedded Trace Macrocell
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-17
Unrestricted Access Non-Confidential
Trace Start/Stop Resource Control - 0xE0041018 No -
TraceEnable Event Write only
0xE0041020 Yes Describes the TraceEnable
enabling event.
[16:14] Boolean function.
[13:7] Resource A.
[6:0] Resource B.
See ETM Event resources on
page 14-22.
TraceEnable Control 1 Write only
0xE0041024 Yes For a description, see page 14-21.
TraceEnable Control 2 Write only
0xE004101C No -
FIFOFULL Region Write only
0xE0041028 No If enabled, FifoFull logic is always
active.
FIFOFULL Level Read/write
0xE004102C Yes The number of bytes left in the
FIFO, below which the
FIFOFULL signal is asserted to
stall the core. Bit [7] of the ETM
Control Register is used to enable
the FIFOFULL output.
ViewData - 0xE0041030 -
0xE004103C
No -
Address Comparators -
0xE0041040 -
0xE004113C
No -
Counters -
0xE0041140 -
0xE004157C
No -
Sequencer -
0xE0041180 -
0xE0041194 ,
0xE0041198
No -
External Outputs -
0xE00411A0 -
0xE00411AC
No -
CID Comparators - 0xE00411B0 -
0xE00411BC
No -
Implementation specific -
0xE00411C0 -
0xE00411DC
No All RAZ. Ignore writes.
Table 14-9 ETM registers (continued)
Name Type Address Present Description

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit