ARM Cortex-M3 User Manual

Signal Descriptions
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. A-5
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VECTADDREN Input Reserved. Must be tied to 1'b0.
DNOTITRANS Input Static tie-off that forces the processor to not permit ICode and DCode AHB
transactions to occur at the same time. This permits a simple bus
multiplexer to be instantiated externally to the processor.
AUXFAULT[31:0] Input Auxiliary fault status information from the system.
IFLUSH Input Reserved. Instruction flush, must be tied to 0.
DBGRESTART Input External restart request.
Table A-3 Miscellaneous signals (continued)
Name Direction Description

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit