ARM Cortex-M3 User Manual

Exceptions
5-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Note
Privilege alone does not prevent corruption of stacks, whether malicious or accidental.
A memory protection scheme of one form or another is required to isolate the user code.
That is, you must prevent the user code from writing to memory it does not own,
including other stacks.
5.4.2 Privilege
Privilege controls access rights, and is decoupled from all other concepts in ARMv7-M.
Code can be privileged, with full access rights, or unprivileged, with limited access
rights. Access rights affect ability to:
• Use or not use certain instructions such as MSR fields.
• Access System Control Space (SCS) registers.
• Access memory or peripherals, based on system design. The processor indicates
to the system whether the code making an access is privileged and so the system
can enforce restrictions on non-privileged access.
• Access rules to memory locations based on an MPU. When fitted with an MPU,
the access restrictions can control what memory can be read, written, and
executed.
Only Thread mode can be unprivileged. All exceptions are privileged.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit