ARM Cortex-M3 User Manual

Introduction
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 1-21
Unrestricted Access Non-Confidential
• DBGRESTART input and DBGRESTARTED output has been added for use in
debugging multi-core systems. See the ARMv7-M Architecture Reference Manual
for more information.
• SLEEPHOLDREQn input and SLEEPHOLDACKn have been added to enable
the extension of SLEEPING. See Extending sleep on page 7-5.
• The APB interface has been upgraded from v2.0 to v3.0. See External private
peripheral interface on page 12-10.
• A new output signal called INTERNALSTATE has been added that enables
observation of some of the internal state of the core if the OBSERVATION
implementation option is used.
• An Auxiliary Control Register has been added with new functionality disable bits
to:
— stop interruption of load/store multiples, divides and multiplies
— stop IT folding
— disable the write buffers in Cortex-M3 for default memory map accesses.
For details on the Auxiliary Control Register see Auxiliary Control Register on
page 8-8.
• The STKALIGN bit reset value in the Configuration and Control Register at
address
0xE000ED14 has been inverted. The reset value is now 1, which means that
the stack frame is 8-byte aligned by default. Configuration Control Register on
page 8-26.
• Addition of a Wake-up Interrupt Controller to minimize logic in always clocked
domain during sleep. For details see Using the Wake-up Interrupt Controller on
page 7-6.
• Addition of FIXHMASTERTYPE pin to prevent debugger marking AHB
transactions as core data side if required.
• Errata fixes to the r1p1 release.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit