ARM Cortex-M3 - Page 156

Nested Vectored Interrupt Controller
8-6 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
MMFR3: Memory Model Feature register3 Read-only 0xE000ED5C 0x00000000 -
ISAR0: ISA Feature register0 Read-only
0xE000ED60 0x01141110 -
ISAR1: ISA Feature register1 Read-only
0xE000ED64 0x02111000 -
ISAR2: ISA Feature register2 Read-only
0xE000ED68 0x21112231 -
ISAR3: ISA Feature register3 Read-only
0xE000ED6C 0x01111110 -
ISAR4: ISA Feature register4 Read-only
0xE000ED70 0x01310102 -
Software Trigger Interrupt Register Write Only
0xE000EF00 -page8-42
Peripheral identification register (PID4) Read-only
0xE000EFD0 0x04 -
Peripheral identification register (PID5) Read-only
0xE000EFD4 0x00 -
Peripheral identification register (PID6) Read-only
0xE000EFD8 0x00 -
Peripheral identification register (PID7) Read-only
0xE000EFDC 0x00 -
Peripheral identification register Bits 7:0 (PID0) Read-only
0xE000EFE0 0x00 -
Peripheral identification register Bits 15:8
(PID1)
Read-only
0xE000EFE4 0xB0 -
Peripheral identification register Bits 23:16
(PID2)
Read-only
0xE000EFE8 0x2B -
Peripheral identification register Bits 31:24
(PID3)
Read-only
0xE000EFEC 0x00 -
Component identification register Bits 7:0
(CID0)
Read Only
0xE000EFF0 0x0D -
Component identification register Bits 15:8
(CID1)
Read-only
0xE000EFF4 0xE0 -
Component identification register Bits 23:16
(CID2)
Read-only
0xE000EFF8 0x05 -
Component identification register Bits 31:24
(CID3)
Read-only 0xE000EFFC 0xB1 -
a. Reset value depends on the number of interrupts defined.
b. Bits [10:8] are reset. The ENDIANESS bit, bit [15], is set at reset by the sampling of BIGEND.
Table 8-1 NVIC registers (continued)
Name of register Type Address
Reset
value
Page