ARM Cortex-M3 User Manual

Nested Vectored Interrupt Controller
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-5
Unrestricted Access Non-Confidential
Irq 224 to 239 Priority Register Read/write 0xE000E4EC 0x00000000 page 8-17
CPUID Base Register Read-only
0xE000ED00 0x412FC230 page 8-18
Interrupt Control State Register Read/write or read-only
0xE000ED04 0x00000000 page 8-19
Vector Table Offset Register Read/write
0xE000ED08 0x00000000 page 8-21
Application Interrupt/Reset Control Register Read/write
0xE000ED0C
0x00000000
b
page 8-22
System Control Register Read/write
0xE000ED10 0x00000000 page 8-25
Configuration Control Register Read/write
0xE000ED14 0x00000000 page 8-26
System Handlers 4-7 Priority Register Read/write
0xE000ED18 0x00000000 page 8-28
System Handlers 8-11 Priority Register Read/write
0xE000ED1C 0x00000000 page 8-28
System Handlers 12-15 Priority Register Read/write
0xE000ED20 0x00000000 page 8-28
System Handler Control and State Register Read/write
0xE000ED24 0x00000000 page 8-29
Configurable Fault Status Registers Read/write
0xE000ED28 0x00000000 page 8-32
Hard Fault Status Register Read/write
0xE000ED2C 0x00000000 page 8-37
Debug Fault Status Register Read/write
0xE000ED30 0x00000000 page 8-38
Mem Manage Address Register Read/write
0xE000ED34 Unpredictable page 8-40
Bus Fault Address Register Read/write
0xE000ED38 Unpredictable page 8-41
Auxiliary Fault Status Register Read/write
0xE000ED3C 0x00000000 page 8-41
PFR0: Processor Feature register0 Read-only
0xE000ED40 0x00000030 -
PFR1: Processor Feature register1 Read-only
0xE000ED44 0x00000200 -
DFR0: Debug Feature register0 Read-only
0xE000ED48 0x00100000 -
AFR0: Auxiliary Feature register0 Read-only
0xE000ED4C 0x00000000 -
MMFR0: Memory Model Feature register0 Read-only
0xE000ED50 0x00000030 -
MMFR1: Memory Model Feature register1 Read-only
0xE000ED54 0x00000000 -
MMFR2: Memory Model Feature register2 Read-only
0xE000ED58 0x00000000 -
Table 8-1 NVIC registers (continued)
Name of register Type Address
Reset
value
Page

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit