ARM Cortex-M3 User Manual

Embedded Trace Macrocell Interface
15-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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ETMIA[31:1] Output No qualifier Instruction address. Indicates the current fetch address of
the opcode in execution, or of the last opcode executed.
You can determine the context by examining:
ETMIVALID
HALTED
SLEEPING.
The ETM examines this net when ETMIVALID is
asserted. The DWT examines this net for PC samples and
bus watching.
ETMFOLD Output ETMIVALID Opcode fold. Indicates that an IT opcode has been folded
in this cycle. PC advances past the current (16-bit) opcode
and the IT instruction (16 bits). This affects the ETMIA.
ETMFLUSH Output No qualifier Flush marker of PC event. A PC modifying opcode has
executed or an interrupt push/pop has started. The ETM
can use this control to complete outstanding packets in
preparation for an ETMIBRANCH event.
ETMFINDBR Output ETMFLUSH Flush is indirect. Marks that the PC cannot deduce the
flush hint destination.
ETMCANCEL Output No qualifier Current opcode in execute has been cancelled. Opcodes
that are interrupted restart or continue on return to this
execution context. These include:
LDR/STR
LDRD/STRD
LDM/STM
U/SMULL
MLA
U/SDIV
MSR
CPSID
Table 15-1 ETM interface ports (continued)
Port name Direction Qualified by Description

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit