ARM Cortex-M3 User Manual

Embedded Trace Macrocell Interface
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 15-5
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ETMISTALL Output No qualifier Indicates that the last instruction signalled by the core has
not yet entered execute. If ETMICANCEL is asserted
with ETMISTALL, it indicates that the stalled
instruction did not execute, and the previous instruction
was cancelled.
ETMTRIGGER[3:0] Output No qualifier Output trigger from DWT. One bit for each of the four
DWT comparators.
ETMTRIGINOTD[3:0] Output No qualifier Output indicates if the ETM is triggered on an instruction
or data match.
Table 15-1 ETM interface ports (continued)
Port name Direction Qualified by Description

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit