ARM Cortex-M3 User Manual

Exceptions
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 5-5
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- 7-10 - Reserved
SVCall 11 Configurable System service call with SVC instruction. This is
synchronous.
Debug Monitor 12 Configurable Debug monitor, when not halting. This is synchronous, but
only active when enabled. It does not activate if lower
priority than the current activation.
-13-Reserved
PendSV 14 Configurable Pendable request for system service. This is asynchronous
and only pended by software.
SysTick 15 Configurable System tick timer has fired. This is asynchronous.
External Interrupt 16 and more Configurable Asserted from outside the core, INTISR[239:0], and fed
through the NVIC (prioritized). These are all asynchronous.
a. You can change the priority of this exception. See System Handler Priority Registers bit assignments on page 8-29. Settable
is an NVIC priority value of 0 to N, where N is the largest priority value implemented. Internally, the highest user-settable
priority (0) is treated as 4. You can enable or disable this fault. See System Handler Control and State Register bit assignments
on page 8-30.
Table 5-1 Exception types (continued)
Exception type Position Priority Description

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit