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Core Debug

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• ICI can be written, though invalid values or when not used on an LDM/STM

causes a fault, as would on return from exception. Changing ICI from a value to

0 causes the underlying LDM/STM to start, not continue.

10.2.3 Debug Core Register Data Register

The purpose of the Debug Core Register Data Register (DCRDR) is to hold data for

reading and writing registers to and from the processor.

The DCRDR:

• is a 32-bit read/write register

• address

0xE000EDF8.

This is the data value written to the register selected by the Debug Register Selector

When the processor receives a request from the Debug Core Register Selector, this

If core register transfers are not being performed, software-based debug monitors can

use this register for communication in non-halting debug. For example, OS RSD and

Real View Monitor. This enables flags and bits to acknowledge state and indicate if

commands have been accepted to, replied to, or accepted and replied to.

10.2.4 Debug Exception and Monitor Control Register

The purpose of the Debug Exception and Monitor Control Register (DEMCR) is:

• Vector catching. That is, to cause debug entry when a specified vector is

committed for execution.

• Debug monitor control.

The DEMCR:

• is a 32-bit read/write register

• has address

0xE000EDFC.

Figure 10-2 on page 10-6 shows the bit assignments in the register.

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ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit