ARM Cortex-M3 User Manual

Revisions
B-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
ETM Trigger Even Register description upgraded Table 14-9 on page 14-16
ETM Status Register description updated
TraceEnable register replaced by Trace Start/Stop Resource
Control
TraceEnable Control 2 register added
Lock Status Register added
Description of FIFOFULL Region Register added
Description of FIFOFULL Level Register updated
Description of CoreSight Trace ID Register updated
Description ETM Control Register implementation bits
expanded
ETM Control Register on page 14-19
Description of TraceEnable Control 1 Register updated TraceEnable Control 1 Register on page 14-21
Description ETM ID Register updated to reflect revision 2 ETM ID Register on page 14-21
Subsection describing ETM Event Resources added ETM Event resources on page 14-22
Subsection describing Cross Trigger Interface added Cross trigger interface on page 14-23
Branch status interface section updated Branch status interface on page 15-6
Note about HADDRICore and HTRANSICore removed Branch status interface on page 15-6
Example of an opcode sequence timing diagram updated Figure 15-9 on page 15-13
Description of APB interface inputs added APB interface on page 17-7
Table B-1 Differences between issue E and issue F (continued)
Change Location

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit