Core Debug
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[17] Read/write
MON_PEND
a
Pend the monitor to activate when priority permits. This can wake up
the monitor through the AHB-AP port. It is the equivalent to C_HALT
for Monitor debug.
This register does not reset on a system reset. It is only reset by a
power-on reset. Software in the reset handler or later, or by the DAP
must enable the debug monitor.
[16] Read/write
MON_EN
a
Enable the debug monitor. When enabled, the System handler priority
register controls its priority level. If disabled, then all debug events go
to Hard fault. C_DEBUGEN in the Debug Halting Control and Statue
register overrides this bit.
Vector catching is semi-synchronous. When a matching event is seen, a
Halt is requested. Because the processor can only halt on an instruction
boundary, it must wait until the next instruction boundary. As a result,
it stops on the first instruction of the exception handler. However, two
special cases exist when a vector catch has triggered:
• If a fault is taken during vectoring, vector read or stack push
error, the halt occurs on the corresponding fault handler, for the
vector error or stack push.
• If a late arriving interrupt comes in during vectoring, it is not
taken. That is, an implementation that supports the late arrival
optimization must suppress it in this case.
[15:11] - - Reserved, SBZP
[10] Read/write
VC_HARDERR
b
Debug trap on Hard Fault.
[9] Read/write
VC_INTERR
b
Debug Trap on interrupt/exception service errors. These are a subset of
other faults and catches before BUSERR or HARDERR.
[8] Read/write
VC_BUSERR
b
Debug Trap on normal Bus error.
[7] Read/write
VC_STATERR
b
Debug trap on Usage Fault state errors.
[6] Read/write
VC_CHKERR
b
Debug trap on Usage Fault enabled checking errors.
[5] Read/write
VC_NOCPERR
b
Debug trap on Usage Fault access to Coprocessor that is not present or
marked as not present in CAR register.
[4] Read/write
VC_MMERR
b
Debug trap on Memory Management faults.
[3:1] - - Reserved, SBZP
[0] Read/write
VC_CORERESET
b
Reset Vector Catch. Halt running system if Core reset occurs.
Table 10-4 Debug Exception and Monitor Control Register (continued)
Bits Type Field Function
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