ARM Cortex-M3 User Manual

Core Debug
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 10-11
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This register manages exception behavior under debug.
Vector catching is only available to halting debug. The upper halfword is for monitor
controls and the lower halfword is for halting exception support.
This register is not reset on a system reset.
This register is reset by a power-on reset. Bits [19:16] are always cleared on a core reset.
The debug monitor is enabled by software in the reset handler or later, or by the
AHB-AP port.
Vector catching is semi-synchronous. When a matching event is seen, a Halt is
requested. Because the processor can only halt on an instruction boundary, it must wait
until the next instruction boundary. As a result, it stops on the first instruction of the
exception handler. However, two special cases exist when a vector catch has triggered:
1. If a fault is taken during a vector read or stack push error the halt occurs on the
corresponding fault handler for the vector error or stack push.
2. If a late arriving interrupt detected during a vector read or stack push error it is not
taken. That is, an implementation that supports the late arrival optimization must
suppress it in this case.
a. This bit clears on a Core Reset.
b. Only usable when C_DEBUGEN = 1.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit