ARM Cortex-M3 User Manual

Contents
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. vii
Unrestricted Access Non-Confidential
Chapter 10 Core Debug
10.1 About core debug ...................................................................................... 10-2
10.2 Core debug registers ................................................................................ 10-3
10.3 Core debug access example .................................................................. 10-12
10.4 Using application registers in core debug ............................................... 10-13
Chapter 11 System Debug
11.1 About system debug ................................................................................. 11-2
11.2 System debug access ............................................................................... 11-3
11.3 System debug programmer’s model ......................................................... 11-5
11.4 FPB ........................................................................................................... 11-6
11.5 DWT ........................................................................................................ 11-13
11.6 ITM .......................................................................................................... 11-30
11.7 AHB-AP ................................................................................................... 11-39
Chapter 12 Bus Interface
12.1 About bus interfaces ................................................................................. 12-2
12.2 AMBA 3 compliance .................................................................................. 12-3
12.3 ICode bus interface ................................................................................... 12-4
12.4 DCode bus interface ................................................................................. 12-6
12.5 System interface ....................................................................................... 12-7
12.6 Unifying the code buses ............................................................................ 12-9
12.7 External private peripheral interface ....................................................... 12-10
12.8 Access alignment .................................................................................... 12-11
12.9 Unaligned accesses that cross regions ................................................... 12-12
12.10 Bit-band accesses ................................................................................... 12-13
12.11 Write buffer ............................................................................................. 12-14
12.12 Memory attributes ................................................................................... 12-15
12.13 AHB timing characteristics ...................................................................... 12-16
Chapter 13 Debug Port
13.1 About the DP ............................................................................................. 13-2
Chapter 14 Embedded Trace Macrocell
14.1 About the ETM .......................................................................................... 14-2
14.2 Data tracing ............................................................................................... 14-7
14.3 ETM resources .......................................................................................... 14-8
14.4 Trace output ............................................................................................ 14-11
14.5 ETM architecture ..................................................................................... 14-12
14.6 ETM programmer’s model ....................................................................... 14-16
Chapter 15 Embedded Trace Macrocell Interface
15.1 About the ETM interface ........................................................................... 15-2
15.2 CPU ETM interface port descriptions ........................................................ 15-3
15.3 Branch status interface ............................................................................. 15-6

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit