ARM Cortex-M3 User Manual

Contents
viii Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Unrestricted Access
Chapter 16 AHB Trace Macrocell Interface
16.1 About the AHB trace macrocell interface .................................................. 16-2
16.2 CPU AHB trace macrocell interface port descriptions .............................. 16-3
Chapter 17 Trace Port Interface Unit
17.1 About the TPIU ......................................................................................... 17-2
17.2 TPIU registers ........................................................................................... 17-8
17.3 Serial wire output connection ................................................................. 17-21
Chapter 18 Instruction Timing
18.1 About instruction timing ............................................................................ 18-2
18.2 Processor instruction timings .................................................................... 18-3
18.3 Load-store timings .................................................................................... 18-7
Chapter 19 AC Characteristics
19.1 Processor timing parameters .................................................................... 19-2
Appendix A Signal Descriptions
A.1 Clocks ......................................................................................................... A-2
A.2 Resets ........................................................................................................ A-3
A.3 Miscellaneous ............................................................................................. A-4
A.4 Interrupt interface ....................................................................................... A-6
A.5 Low power interface ................................................................................... A-7
A.6 ICode interface ........................................................................................... A-8
A.7 DCode interface .......................................................................................... A-9
A.8 System bus interface ................................................................................ A-10
A.9 Private Peripheral Bus interface ............................................................... A-11
A.10 ITM interface ............................................................................................. A-12
A.11 AHB-AP interface ..................................................................................... A-13
A.12 ETM interface ........................................................................................... A-14
A.13 AHB Trace Macrocell interface ................................................................. A-16
A.14 Test interface ............................................................................................ A-17
A.15 WIC interface ............................................................................................ A-18
Appendix B Revisions
Glossary

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit