ARM Cortex-M3 User Manual

ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. ix
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List of Tables
Cortex-M3 Technical Reference Manual
Change History ............................................................................................................. ii
Table 2-1 Application Program Status Register bit assignments .............................................. 2-6
Table 2-2 Interrupt Program Status Register bit assignments .................................................. 2-7
Table 2-3 Bit functions of the EPSR .......................................................................................... 2-8
Table 2-4 16-bit Cortex-M3 instruction summary .................................................................... 2-13
Table 2-5 32-bit Cortex-M3 instruction summary .................................................................... 2-16
Table 3-1 NVIC registers ........................................................................................................... 3-2
Table 3-2 Core debug registers ................................................................................................. 3-5
Table 3-3 Flash patch register summary ................................................................................... 3-6
Table 3-4 DWT register summary ............................................................................................. 3-7
Table 3-5 ITM register summary ............................................................................................... 3-9
Table 3-6 AHB-AP register summary ...................................................................................... 3-10
Table 3-7 Summary of Debug interface port registers ............................................................ 3-10
Table 3-8 MPU registers ......................................................................................................... 3-11
Table 3-9 TPIU registers ......................................................................................................... 3-12
Table 3-10 ETM registers .......................................................................................................... 3-13
Table 4-1 Memory interfaces ..................................................................................................... 4-3
Table 4-2 Memory region permissions ...................................................................................... 4-4
Table 4-3 ROM table ................................................................................................................. 4-7
Table 5-1 Exception types ......................................................................................................... 5-4
Table 5-2 Priority-based actions of exceptions ......................................................................... 5-6
Table 5-3 Priority grouping ........................................................................................................ 5-8
Table 5-4 Exception entry steps .............................................................................................. 5-12

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit