ARM Cortex-M3 User Manual

List of Tables
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Table 5-5 Exception exit steps ................................................................................................ 5-17
Table 5-6 Exception return behavior ....................................................................................... 5-19
Table 5-7 Reset actions .......................................................................................................... 5-20
Table 5-8 Reset boot-up behavior .......................................................................................... 5-21
Table 5-9 Transferring to exception processing ...................................................................... 5-24
Table 5-10 Faults ...................................................................................................................... 5-28
Table 5-11 Debug faults ............................................................................................................ 5-30
Table 5-12 Fault status and fault address registers .................................................................. 5-31
Table 5-13 Privilege and stack of different activation levels ..................................................... 5-32
Table 5-14 Exception transitions ............................................................................................... 5-32
Table 5-15 Exception subtype transitions ................................................................................. 5-33
Table 6-1 Cortex-M3 processor clocks ..................................................................................... 6-2
Table 6-2 Cortex-M3 macrocell clocks ...................................................................................... 6-2
Table 6-3 Reset inputs .............................................................................................................. 6-4
Table 6-4 Reset modes ............................................................................................................. 6-5
Table 7-1 Supported sleep modes ............................................................................................ 7-3
Table 8-1 NVIC registers .......................................................................................................... 8-3
Table 8-2 Interrupt Controller Type Register bit assignments .................................................. 8-8
Table 8-3 Auxiliary Control Register bit assignments ............................................................... 8-9
Table 8-4 SysTick Control and Status Register bit assignments ............................................ 8-10
Table 8-5 SysTick Reload Value Register bit assignments .................................................... 8-11
Table 8-6 SysTick Current Value Register bit assignments .................................................... 8-12
Table 8-7 SysTick Calibration Value Register bit assignments .............................................. 8-12
Table 8-8 Interrupt Set-Enable Register bit assignments ....................................................... 8-14
Table 8-9 Interrupt Clear-Enable Register bit assignments .................................................... 8-14
Table 8-10 Interrupt Set-Pending Register bit assignments ..................................................... 8-15
Table 8-11 Interrupt Clear-Pending Registers bit assignments ................................................ 8-16
Table 8-12 Active Bit Register bit assignments ........................................................................ 8-16
Table 8-13 Interrupt Priority Registers 0-31 bit assignments .................................................... 8-18
Table 8-14 CPUID Base Register bit assignments ................................................................... 8-18
Table 8-15 Interrupt Control State Register bit assignments .................................................... 8-20
Table 8-16 Vector Table Offset Register bit assignments ........................................................ 8-22
Table 8-17 Application Interrupt and Reset Control Register bit assignments ......................... 8-23
Table 8-18 System Control Register bit assignments ............................................................... 8-26
Table 8-19 Configuration Control Register bit assignments ..................................................... 8-27
Table 8-20 System Handler Priority Registers bit assignments ................................................ 8-29
Table 8-21 System Handler Control and State Register bit assignments ................................. 8-30
Table 8-22 Memory Manage Fault Status Register bit assignments ........................................ 8-33
Table 8-23 Bus Fault Status Register bit assignments ............................................................. 8-35
Table 8-24 Usage Fault Status Register bit assignments ......................................................... 8-36
Table 8-25 Hard Fault Status Register bit assignments ........................................................... 8-38
Table 8-26 Debug Fault Status Register bit assignments ......................................................... 8-39
Table 8-27 Memory Manage Fault Address Register bit assignments ..................................... 8-40
Table 8-28 Bus Fault Address Register bit assignments .......................................................... 8-41
Table 8-29 Auxiliary Fault Status Register bit assignments ...................................................... 8-42
Table 8-30 Software Trigger Interrupt Register bit assignments .............................................. 8-42
Table 9-1 MPU registers ........................................................................................................... 9-3

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit