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Embedded Trace Macrocell

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TraceEnable Control 1 Register

The TraceEnable Control 1 Register is one of the registers that configures TraceEnable.

Only bit [25], Trace start/stop enable, is implemented as follows:

• 0 - Tracing is unaffected by the trace start/stop logic.

• 1 - Tracing is controlled by the trace on and off addresses configured for the trace

start/stop logic.

The trace start/stop resource (resource

0x5F

) is unaffected by the value of this bit.

ETM ID Register

The ETM ID Register holds the ETM architecture variant, and precisely defines the

programmer’s model for the ETM.

Reset value:

0x4114F242

This indicates:

• ARM implementor

• special branch encoding, affects bits [7:6] of each byte

• 32-bit Thumb instruction supported

• core family is found elsewhere

• ETMv3.4

• implementation revision 2.

Configuration Code Extension Register

The Configuration Code Extension Register holds additional bits for ETM

configuration code. It describes the extended external inputs.

Reset value:

0x00018800

This register indicates:

• start/stop block uses embedded In Circuit Emulator (ICE) inputs

• four embedded ICE inputs

• no data comparisons supported

• all registers are readable

• no extended external input supported.

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ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit