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Embedded Trace Macrocell

Non-Confidential

Unrestricted Access

• [11] ETMEN

• [10] ETM Programming

• [9] Debug request control

• [8] Branch Output

• [7] Stall Processor

• [6:4] PortSize [2:0]

• [0] ETM Power Down.

All other bits RAZ, ignore writes.

Configuration Code Register

The ETM Configuration Code Register enables the debugger to read the

implementation-specific configuration of the ETM.

Reset value:

0x8C800000

Bits [22:20] are fixed at 0 and not supplied by the ASIC. Bits [18:17] are supplied by

the MAXEXTIN[1:0] input bus, and read the lower value of MAXEXTIN and the

number 2 (the number of EXTINs). This indicates:

• software accesses supported

• trace start/stop block present

• no CID comparators

• FIFOFULL logic is present

• no external outputs

• 0-2 external inputs (controlled by MAXEXTIN)

• no sequencer

• no counters

• no MMDs

• no data comparators

• no address comparator pairs.

System Configuration Register

The System Configuration Register shows the ETM features supported by the ASIC.

Reset value:

0x00020D09

Bits [11:10] are implemented as normal. Bits [9], [2:0] are fixed as 4’b0001.

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ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit