ARM Cortex-M3 User Manual

Embedded Trace Macrocell
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-19
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14.6.3 Description of ETM registers
An additional description of some of the ETM registers is given in the following
sections. See the ARM Embedded Trace Macrocell Architecture Specification for more
information.
ETM Control Register
The ETM Control Register controls general operation of the ETM, such as whether
tracing is enabled.
Reset value:
0x00002411
Implemented bits:
• [21] Port Size[3]
• [17:16] Port Mode[1:0]
• [13] Port Mode[2]
Authentication Status Read only 0xE0041FB8 Yes Implemented as normal.
Device Type Read only
0xE0040FCC Yes Reset value: 0x13 .
Peripheral ID 4 Read only
0xE0041FD0 Yes 0x04
Peripheral ID 5 Read only 0xE0041FD4 Yes 0x00
Peripheral ID 6 Read only 0xE0041FD8 Yes 0x00
Peripheral ID 7 Read only 0xE0041FDC Yes 0x00
Peripheral ID 0 Read only 0xE0041FE0 Yes 0x24
Peripheral ID 1 Read only 0xE0041FE4 Yes 0xB9
Peripheral ID 2 Read only 0xE0041FE8 Yes 0x2B
Peripheral ID 3 Read only 0xE0041FEC Yes 0x00
Component ID 0 Read only 0xE0041FF0 Yes 0x0D
Component ID 1 Read only 0xE0041FF4 Yes 0x90
Component ID 2 Read only 0xE0041FF8 Yes 0x05
Component ID 3 Read only 0xE0041FFC Yes 0xB1
Table 14-9 ETM registers (continued)
Name Type Address Present Description

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit