ARM Cortex-M3 User Manual

Introduction
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 1-13
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The names of the pipeline stages and their functions are:
Fe Instruction fetch where data is returned from the instruction memory.
De Instruction decode, generation of LSU address using forwarded register
ports, and immediate offset or LR register branch forwarding.
Ex Instruction execute, single pipeline with multi-cycle stalls, LSU
address/data pipelining to AHB interface, multiply/divide, and ALU with
branch result.
The pipeline structure provides a pipelined 2-cycle memory access with no ALU usage
penalty, address generation forwarding for pointer indirection.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit