ARM Cortex-M3 User Manual

ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. A-1
Unrestricted Access Non-Confidential
Appendix A
Signal Descriptions
This appendix lists and describes the processor interface signals. It contains the
following sections:
• Clocks on page A-2
• Resets on page A-3
• Miscellaneous on page A-4
• Interrupt interface signals on page A-6
• Low power interface on page A-7
• ICode interface on page A-8
• DCode interface on page A-9
• System bus interface on page A-10
• Private Peripheral Bus interface on page A-11
• ITM interface on page A-12
• AHB-AP interface on page A-13
• ETM interface on page A-14
• AHB Trace Macrocell interface on page A-16
• Test interfa ce on page A-17
• WIC interface on page A-18.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit