ARM Cortex-M3 User Manual

Clocking and Resets
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 6-3
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Note
SWCLKTCK, DBGCLK, and TRACECLKIN only require to be driven if your
implementation contains Serial Wire JTAG Debug Port (SWJ-DP), Serial Wire Debug
Port (SW-DP), and TPIU blocks respectively. Otherwise, the clock inputs must be tied
off.
Note
The processor also contains a STCLK input. This port is not a clock. It is a reference
input for the SysTick counter, and it must be less than half the frequency of FCLK.
STCLK is synchronized internally by the processor to FCLK.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit