ARM Cortex-M3 User Manual

Nested Vectored Interrupt Controller
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-31
Unrestricted Access Non-Confidential
The active bits indicate if any of the system handlers are active, running now, or stacked
because of pre-emption. This information is used for debugging and is also used by the
application handlers. The pend bits are only set when a fault that cannot be retried has
been deferred because of late arrival of a higher priority interrupt.
Caution
You can write, clear, or set the active bits, but you must only do this with extreme
caution. Clearing and setting these bits does not repair stack contents nor clean up other
data structures. It is intended that context switchers use clearing and setting to save a
thread’s context, even when in a fault handler. The most common case is to save the
context of a thread that is in an SVCall handler or UsageFault handler, for undefined
instruction and coprocessor emulation.
The model for doing this is to save the current state, switch out the stack containing the
handler’s context, load the state of the new thread, switch in the new thread’s stacks, and
then return to the thread. The active bit of the current handler must never be cleared,
because the IPSR is not changed to reflect this. Only use it to change stacked active
handlers.
As indicated, the SVCALLPENDED and BUSFAULTPENDED bits are set when the
corresponding handler is held off by a late arriving interrupt. These bits are not cleared
until the underlying handler is actually invoked. That is, if a stack error or vector read
error occurs before the SVCall or BusFault handler is started, the bits are not cleared.
This enables the push-error or vector-read-error handler to choose to clear them or retry.
[10] PENDSVACT Reads as 1 if PendSV is active.
[9] - Reserved
[8] MONITORACT Reads as 1 if the Monitor is active.
[7] SVCALLACT Reads as 1 if SVCall is active.
[6:4] - Reserved
[3] USGFAULTACT Reads as 1 if UsageFault is active.
[2] - Reserved
[1] BUSFAULTACT Reads as 1 if BusFault is active.
[0] MEMFAULTACT Reads as 1 if MemManage is active.
Table 8-21 System Handler Control and State Register bit assignments
Bits Field Function

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit