ARM Cortex-M3 User Manual

Glossary
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BE-32 Big-endian view of memory in a word-invariant system.
See also BE-8, LE, Byte-invariant and Word-invariant.
Big-endian Byte ordering scheme in which bytes of decreasing significance in a data word are
stored at increasing addresses in memory.
See also Little-endian and Endianness.
Big-endian memory Memory in which:
• a byte or halfword at a word-aligned address is the most significant byte or
halfword within the word at that address
• a byte at a halfword-aligned address is the most significant byte within the
halfword at that address.
See also Little-endian memory.
Boundary scan chain
A boundary scan chain is made up of serially-connected devices that implement
boundary scan technology using a standard JTAG TAP interface. Each device contains
at least one TAP controller containing shift registers that form the chain connected
between TDI and TDO, through which test data is shifted. Processors can contain
several shift registers to enable you to access selected parts of the device.
Branch folding Branch folding is a technique where the branch instruction is completely removed from
the instruction stream presented to the execution pipeline.
Breakpoint A breakpoint is a mechanism provided by debuggers to identify an instruction at which
program execution is to be halted. Breakpoints are inserted by the programmer to enable
inspection of register contents, memory locations, variable values at fixed points in the
program execution to test that the program is operating correctly. Breakpoints are
removed after the program is successfully tested.
See also Watchpoint.
Burst A group of transfers to consecutive addresses. Because the addresses are consecutive,
there is no requirement to supply an address for any of the transfers after the first one.
This increases the speed at which the group of transfers can occur. Bursts over AMBA
are controlled using signals to indicate the length of the burst and how the addresses are
incremented.
See also Beat.
Byte An 8-bit data item.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit