ARM Cortex-M3 User Manual

Glossary
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. Glossary-7
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Halt mode One of two mutually exclusive debug modes. In halt mode all processor execution halts
when a breakpoint or watchpoint is encountered. All processor state, coprocessor state,
memory and input/output locations can be examined and altered by the JTAG interface.
See also Monitor debug-mode.
Host A computer that provides data and other services to another computer. Especially, a
computer providing debugging services to a target being debugged.
HTM See AHB Trace Macrocell.
ICode Memory Memory space at 0x00000000 to 0x1FFFFFFF .
Illegal instruction An instruction that is architecturally Undefined.
Implementation-defined
The behavior is not architecturally defined, but is defined and documented by individual
implementations.
Implementation-specific
The behavior is not architecturally defined, and does not have to be documented by
individual implementations. Used when there are a number of implementation options
available and the option chosen does not affect software compatibility.
Instruction cycle count
The number of cycles for which an instruction occupies the Execute stage of the
pipeline.
Instrumentation trace
A component for debugging real-time systems through a simple memory-mapped trace
interface, providing
printf style debugging.
Intelligent Energy Management (IEM)
A technology that enables dynamic voltage scaling and clock frequency variation to be
used to reduce power consumption in a device.
Internal PPB PPB memory space at 0xE0000000 to 0xE003FFFF .
Interrupt service
routine
A program that control of the processor is passed to when an interrupt occurs.
Interrupt vector One of a number of fixed addresses in low memory that contains the first instruction of
the corresponding interrupt service routine.
Joint Test Action Group (JTAG)
The name of the organization that developed standard IEEE 1149.1. This standard
defines a boundary-scan architecture used for in-circuit testing of integrated circuit
devices. It is commonly known by the initials JTAG.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit