ARM Cortex-M3 User Manual

Glossary
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SWJ-DP See Serial-Wire JTAG Debug Port.
Synchronization primitive
The memory synchronization primitive instructions are those instructions that are used
to ensure memory synchronization. That is, the LDREX and STREX instructions.
System memory Memory space at 0x20000000 to 0xFFFFFFFF , excluding PPB space at 0xE0000000 to
0xE00FFFFF .
TAP See Test access port.
Test Access Port (TAP)
The collection of four mandatory and one optional terminals that form the input/output
and control interface to a JTAG boundary-scan architecture. The mandatory terminals
are TDI, TDO, TMS, and TCK. The optional terminal is TRST. This signal is
mandatory in ARM cores because it is used to reset the debug logic.
Thread Control
Block
A data structure used by an operating system kernel to maintain information specific to
a single thread of execution.
Thumb instruction A halfword that specifies an operation for an ARM processor in Thumb state to
perform. Thumb instructions must be halfword-aligned.
Thumb state A processor that is executing Thumb (16-bit) halfword aligned instructions is operating
in Thumb state.
TPA See Trace Port Analyzer.
TPIU See Trace Port Interface Unit.
Trace Port Interface Unit (TPIU)
Drains trace data and acts as a bridge between the on-chip trace data and the data stream
captured by a TPA.
Unaligned A data item stored at an address that is not divisible by the number of bytes that defines
the data size is said to be unaligned. For example, a word stored at an address that is not
divisible by four.
UNP See Unpredictable.
Unpredictable For reads, the data returned when reading from this location is unpredictable. It can have
any value. For writes, writing to this location causes unpredictable behavior, or an
unpredictable change in device configuration. Unpredictable instructions must not halt
or hang the processor, or any part of the system.
Wake-up Interrupt
Controller (WIC)
The Wake-up Interrupt Controller provides significantly reduced gate count interrupt
detection and prioritization logic.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit