Xilinx virtex-5 fpga User Manual

120 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 4: Block RAM
Additional Block RAM Features in Virtex-5 Devices
Optional Output Registers
The optional output registers improve design performance by eliminating routing delay to
the CLB flip-flops for pipelined operation. An independent clock and clock enable input is
provided for these output registers. As a result the output data registers hold the value
independent of the input register operation. Figure 4-5 shows the optional output register.
Independent Read and Write Port Width Selection
Each block RAM port has control over data width and address depth (aspect ratio). The
true dual-port block RAM in Virtex-5 FPGAs extends this flexibility to Read and Write
where each individual port can be configured with different data bit widths. For example,
port A can have a 36-bit Read width and a 9-bit Write width, and port B can have a 18-bit
Read width and a 36-bit Write width. See “Block RAM Attributes,” page 128.
If the Read port width differs from the Write port width, and is configured in
WRITE_FIRST mode, then DO shows valid new data for all the enabled write bytes. The
DO port outputs the original data stored in memory for all not enabled bytes.
Independent Read and Write port width selection increases the efficiency of implementing
a content addressable memory (CAM) in block RAM. This option is available for all
Virtex-5 FPGA true dual-port RAM port sizes and modes.
X-Ref Target - Figure 4-5
Figure 4-5: Block RAM Logic Diagram (One Port Shown)
Register
Optional
Inverter
Latches
Register
Address
DI
WE
EN
CLK
Write
Strobe
Read
Strobe
QDQD
DO
Control Engine
Configurable Options
UG190_4_06_040606
Memory
Array
(common to
both ports)
Latch
Enable

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English