Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 67
UG190 (v5.0) June 19, 2009
DCM Design Guidelines
• Downstream DCMs when two or more DCMs are cascaded
• DCMs with external feedback
• DCMs with an external CLKIN that does not come from a dedicated clock input pin.
Source-Synchronous Setting
When DESKEW_ADJUST is set to source-synchronous mode, the DCM feedback delay
element is set to zero. As shown in Figure 2-4, in source-synchronous mode, the DCM
clock feedback delay element is set to minimize the sampling window. This results in a
more positive hold time and a longer clock-to-out compared to system-synchronous mode.
The source-synchronous switching characteristics section in the Virtex-5 FPGA Data Sheet
reflects the various timing parameters for the source-synchronous design when the DCM
is in source-synchronous mode.
Characteristics of the Deskew Circuit
• Eliminate clock distribution delay by effectively adding one clock period delay.
• Clocks are deskewed to within CLKOUT_PHASE, specified in the Virtex-5 FPGA Data
Sheet.
• Eliminate on-chip as well as off-chip clock delay.
• No restrictions on the delay in the feedback clock path.
• Requires a continuously running input clock.
• Adapts to a wide range of frequencies. However, once locked to a frequency, large
input frequency variations are not tolerated.
• Does not eliminate jitter. The deskew circuit output jitter is the accumulation of input
jitter and any added jitter value due to the deskew circuit.
• The completion of configuration can be delayed until after DCM locks to guarantee
the system clock is established prior to initiating the device.
Frequency Synthesis
The DCM provides several flexible methods for generating new clock frequencies. Each
method has a different operating frequency range and different AC characteristics. The
CLK2X and CLK2X180 outputs double the clock frequency. The CLKDV output provides a
divided output clock (lower frequency) with division options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5,
5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16.
The DCM also offers fully digital, dedicated frequency-synthesizer outputs CLKFX and its
opposite phase CLKFX180. The output frequency can be any function of the input clock
frequency described by M ÷ D, where M is the multiplier (numerator) and D is the divisor
(denominator).
The frequency synthesized outputs can drive the global-clock routing networks within the
device. The well-buffered global-clock distribution network minimizes clock skew due to
differences in distance or loading.
Frequency Synthesis Operation
The DCM clock output CLKFX is any M ÷ D factor of the clock input to the DCM.
Specifications for M and D, as well as input and output frequency ranges for the frequency
synthesizer, are provided in the Virtex-5 FPGA Data Sheet.

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English