Xilinx virtex-5 fpga - HSTL Class IV (1.8 V)

Virtex-5 FPGA User Guide www.xilinx.com 271
UG190 (v5.0) June 19, 2009
Specific Guidelines for I/O Supported Standards
HSTL Class IV (1.8V)
Figure 6-63 shows a sample circuit illustrating a valid unidirectional termination technique
for HSTL Class IV (1.8V).
Figure 6-64 shows a sample circuit illustrating a valid bidirectional termination technique
for HSTL Class IV (1.8V).
X-Ref Target - Figure 6-63
Figure 6-63: HSTL Class IV (1.8V) with Unidirectional Termination
Z
0
IOB
IOB
HSTL_IV_18
HSTL_IV_18
ug190_6_60_030306
V
TT
= 1.8V
R
P
= Z
0
= 50Ω
V
TT
= 1.8V
R
P
= Z
0
= 50Ω
Z
0
IOB
IOB
HSTL_IV_DCI_18
HSTL_IV_DCI_18
V
CCO
= 1.8V
R
VRP
= Z
0
= 50Ω
V
REF
= 1.1V
+
–
V
REF
= 1.1V
+
–
External Termination
DCI
V
CCO
= 1.8V
R
VRP
= Z
0
= 50Ω