Xilinx virtex-5 fpga

202 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 5: Configurable Logic Blocks (CLBs)
Timing Parameters
Table 5-7 shows the general slice timing parameters for a majority of the paths in
Figure 5-25.
Table 5-7: General Slice Timing Parameters
Parameter Function Description
Combinatorial Delays
T
ILO
(1)
A/B/C/D inputs to A/B/C/D
outputs
Propagation delay from the A/B/C/D inputs of
the slice, through the look-up tables (LUTs), to the
A/B/C/D outputs of the slice (six-input
function).
T
ILO_2
A/B/C/D inputs to
AMUX/CMUX outputs
Propagation delay from the A/B/C/D inputs of
the slice, through the LUTs and
F7AMUX/F7BMUX to the AMUX/CMUX
outputs (seven-input function).
T
ILO_3
A/B/C/D inputs to BMUX
output
Propagation delay from the A/B/C/D inputs of
the slice, through the LUTs, F7AMUX/F7BMUX,
and F8MUX to the BMUX output (eight-input
function).
Sequential Delays
T
CKO
FF Clock (CLK) to
AQ/BQ/CQ/DQ outputs
Time after the clock that data is stable at the
AQ/BQ/CQ/DQ outputs of the slice sequential
elements (configured as a flip-flop).
T
CKLO
Latch Clock (CLK) to
AQ/BQ/CQ/DQ outputs
Time after the clock that data is stable at the
XQ/YQ outputs of the slice sequential elements
(configured as a latch).
Setup and Hold Times for Slice Sequential Elements
(2)
T
DICK
/T
CKDI
AX/BX/CX/DX inputs Time before/after the CLK that data from the
AX/BX/CX/DX inputs of the slice must be stable
at the D input of the slice sequential elements
(configured as a flip-flop).
T
CECK
/T
CKCE
CE input Time before/after the CLK that the CE input of
the slice must be stable at the CE input of the slice
sequential elements (configured as a flip-flop).
T
SRCK
/T
CKSR
SR/BY input Time before/after the CLK that the SR (Set/Reset)
and the BY (Rev) inputs of the slice must be stable
at the SR/Rev inputs of the slice sequential
elements (configured as a flip-flop).
Set/Reset
T
RPW
Minimum Pulse Width for the SR (Set/Reset) and
BY (Rev) pins.
T
RQ
Propagation delay for an asynchronous Set/Reset
of the slice sequential elements. From the SR/BY
inputs to the AQ/BQ/CQ/DQ outputs.
F
TOG
Toggle Frequency – Maximum frequency that a
CLB flip-flop can be clocked: 1 / (T
CH
+ T
CL
).
Notes:
1. This parameter includes a LUT configured as two five-input functions.
2. T
XXCK
= Setup Time (before clock edge), and T
CKXX
= Hold Time (after clock edge).