Xilinx virtex-5 fpga

270 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
HSTL Class III (1.8V)
Figure 6-62 shows a sample circuit illustrating a valid termination technique for HSTL
Class III (1.8V).
Table 6-25 lists the HSTL Class III (1.8V) DC voltage specifications.
X-Ref Target - Figure 6-62
Figure 6-62: HSTL Class III (1.8V) Termination
Table 6-25: HSTL Class III (1.8V) DC Voltage Specifications
Min Typ Max
V
CCO
1.7 1.8 1.9
V
REF
(2)
– 1.1 –
V
TT
–V
CCO
–
V
IH
V
REF
+0.1 – –
V
IL
––V
REF
–0.1
V
OH
V
CCO
–0.4 – –
V
OL
– – 0.4
I
OH
at V
OH
(mA)
(1)
–8 – –
I
OL
at V
OL
(mA)
(1)
24 – –
Notes:
1. V
OL
and V
OH
for lower drive currents are sample tested.
2. Per EIA/JESD8-6, “The value of V
REF
is to be selected by the user to provide optimum noise margin in
the use conditions specified by the user.”
Z
0
IOB
IOB
HSTL_III_18
HSTL_III_18
ug190_6_59_030306
V
TT
= 1.8V
R
P
= Z
0
= 50Ω
Z
0
IOB
IOB
HSTL_III_DCI_18 HSTL_III_DCI_18
V
CCO
= 1.8V
R
VRP
= Z
0
= 50Ω
V
REF
= 1.1V
+
–
V
REF
= 1.1V
+
–
External Termination
DCI