Xilinx virtex-5 fpga User Manual

340 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 7: SelectIO Logic Resources
IDELAYCTRL Usage and Design Guidelines
This section describes using the IDELAYCTRL modules, design guidelines, and
recommended usage in Virtex-5 devices.
Instantiating IDELAYCTRL Without LOC Constraints
When instantiating IDELAYCTRL without LOC constraints, the user must instantiate only
one instance of IDELAYCTRL in the HDL design code. The implementation tools auto-
replicate IDELAYCTRL instances throughout the entire device. When IDELAYCTRL
instances are replicated to clock regions but not used, the extra instances are trimmed out
of the design automatically by the ISE software. The signals connected to the RST and
REFCLK input ports of the instantiated IDELAYCTRL instance are connected to the
corresponding input ports of the replicated IDELAYCTRL instances.
There are two special cases:
1. When the RDY port is ignored, the RDY signals of all the replacement IDELAYCTRL
instances are left unconnected.
The VHDL and Verilog use models for instantiating an IDELAYCTRL primitive
without LOC constraints leaving the RDY output port unconnected are provided in
the Libraries Guide.
The resulting circuitry after instantiating the IDELAYCTRL components is illustrated
in Figure 7-18.
X-Ref Target - Figure 7-17
Figure 7-17: Relative Locations of IDELAYCTRL Modules
1 Clock Region
CMT
CMT
Configuration
Left I/O
Column
Center I/O
Column
Right I/O
Column
IDELAYCTRL
ug190_7_12_041206

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English