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Xilinx virtex-5 fpga User Manual

Xilinx virtex-5 fpga
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212 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 5: Configurable Logic Blocks (CLBs)
Instantiating several distributed RAM primitives can be used to implement wide memory
blocks.
Port Signals
Each distributed RAM port operates independently of the other while reading the same set
of memory cells.
Clock – WCLK
The clock is used for the synchronous write. The data and the address input pins have
setup times referenced to the WCLK pin.
Enable – WE/WED
The enable pin affects the write functionality of the port. An active write enable prevents
any writing to memory cells. An active write enable causes the clock edge to write the data
input signal to the memory location pointed to by the address inputs.
Address – A[#:0], DPRA[#:0], and ADDRA[#:0] – ADDRD[#:0]
The address inputs A[#:0] (for single-port and dual-port), DPRA[#:0] (for dual-port), and
ADDRA[#:0] – ADDRD[#:0] (for quad-port) select the memory cells for read or write. The
width of the port determines the required address inputs. Some of the address inputs are
not buses in VHDL or Verilog instantiations. Table 5-11 summarizes the function of each
address pins.
Data In – D, DID[#:0]
The data input D (for single-port and dual-port) and DID[#:0] (for quad-port) provide the
new data value to be written into the RAM.
Data Out – O, SPO, DPO and DOA[#:0] – DOD[#:0]
The data out O (single-port or SPO), DPO (dual-port), and DOA[#:0] – DOD[#:0] (quad-
port) reflects the contents of the memory cells referenced by the address inputs. Following
an active write clock edge, the data out (O, SPO, or DOD[#:0]) reflects the newly written
data.
X-Ref Target - Figure 5-32
Figure 5-32: Single-Port, Dual-Port, and Quad-Port Distributed RAM Primitives
RAM#X1S
UG190_5_32_112108
D
O
WE
WCLK
A[#:0]
SPO DOD[#:0]
RAM#X1D
D
DPO
R/W Port
Read Port
WE
WCLK
A[#:0]
DPRA[#:0]
RAM#M
DI[A:D][#:0]
DOC[#:0]
R/W Port
Read Port
Read Port
Read Port
WE
WCLK
ADDRD[#:0]
ADDRC[#:0]
DOB[#:0]ADDRB[#:0]
DOA[#:0]ADDRA[#:0]

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Xilinx virtex-5 fpga Specifications

General IconGeneral
BrandXilinx
Modelvirtex-5 fpga
CategoryComputer Hardware
LanguageEnglish

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