Xilinx virtex-5 fpga User Manual

162 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 4: Block RAM
Block RAM and FIFO ECC Port Descriptions
Table 4-21 lists and describes the block RAM ECC I/O port names.
Table 4-21: Block RAM ECC Port Names and Descriptions
Port Name Direction Signal Description
DI[63:0] Input Data input bus.
DIP[7:0] Input Data input parity bus. Used in decode-only mode to input the precalculated ECC
parity bits.
WRADDR[8:0] Input Write address bus.
RDADDR[8:0] Input Read address bus.
WREN Input Write enable. When WREN = 1, data will be written into memory. When WREN = 0,
write is disabled
RDEN Input Read enable. When RDEN = 1, data will be read from memory. When RDEN = 0, read
is disabled.
SSR Input Not supported when using the block RAM ECC primitive. Always connect to GND.
WRCLK Input Clock for write operations.
RDCLK Input Clock for read operations.
DO[63:0] Output Data output bus.
DOP[7:0] Output Data output parity bus. Used in encode-only mode to output the stored ECC parity
bits.
SBITERR
(1)
Output Single-bit error status.
DBITERR
(1)
Output Double-bit error status.
ECCPARITY[7:0] Output ECC encoder output bus.
Notes:
1. Hamming code implemented in the block RAM ECC logic detects one of three conditions: no detectable error, single-bit error
detected and corrected on DO (but not corrected in the memory), and double-bit error detected without correction. SBITERR and
DBITERR indicate these three conditions.

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English