Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 129
UG190 (v5.0) June 19, 2009
Block RAM Attributes
Content Initialization - INITP_xx
INITP_xx attributes define the initial contents of the memory cells corresponding to
DIP/DOP buses (parity bits). By default these memory cells are also initialized to all zeros.
The initialization attributes represent the memory contents of the parity bits. The eight
initialization attributes are INITP_00 through INITP_07 for the RAMB18. The 16
initialization attributes are INITP_00 through INITP_0F for the RAMB36. Each INITP_xx is
a 64-digit hex-encoded bit vector with a regular INIT_xx attribute behavior. The same
formula can be used to calculate the bit positions initialized by a particular INITP_xx
attribute.
Output Latches Initialization - INIT (INIT_A or INIT_B)
The INIT (single-port) or INIT_A and INIT_B (dual-port) attributes define the output
latches or output register values after configuration. The width of the INIT (INIT_A and
INIT_B) attribute is the port width, as shown in Table 4-10. These attributes are hex-
encoded bit vectors, and the default value is 0. In cascade mode, both the upper and lower
block RAM should be initialized to the same value.
Table 4-9: Block RAM Initialization Attributes
Attribute
Memory Location
From To
INIT_00 255 0
INIT_01 511 256
INIT_02 767 512
…… …
INIT_0E 3839 3584
INIT_0F 4095 3840
INIT_10 4351 4096
…… …
INIT_1F 8191 7936
INIT_20 8447 8192
…… …
INIT_2F 12287 12032
INIT_30 12543 12288
…… …
INIT_3F 16383 16128
…… …
INIT_7F 32767 32512

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English