Xilinx virtex-5 fpga User Manual

166 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 4: Block RAM
Standard ECC
Set by Attributes
EN_ECC_READ = TRUE
EN_ECC_WRITE = TRUE
Standard ECC Write
At time T1W, DI[63:0] = A is written into memory location a. The corresponding 8 bits of
ECC parity PA (hex) are generated internally, appended to the 64 data bits, and written into
the memory. Immediately after the write, the parity value PA appears at output
ECCPARITY[7:0]. Since ECC parity is generated internally, DIP[7:0] pins are not used.
Similarly, at time T2W and T3W, DI[63:0] = B and C, together with their corresponding
parity bits PB (hex) and PC (hex) are written into memory locations b and c. PB and PC
appear at output ECCPARITY[7:0] shortly after T2W and T3W.
Standard ECC Read
At time T1R, the 72-bit memory content, consisting 64 bits of data A and 8 bits of parity PA
(hex), of address location a is read and decoded internally. If there is no error, the original
data and parity are output at DO[63:0] and DOP[7:0]. If there is a single-bit error in either
the data or the parity, the error is corrected, and SBITERR is High. If there is a double-bit
error in the data and parity, the error is not corrected. The original data and parity is output
and DBITERR is High.
If attribute DO_REG is set to 0, DO[63:0] = A and DOP[7:0] = PA shortly after T1R.
Similarly, at time T2R and T3R, the memory content at address locations b and c are read
and decoded at DO[63:0] and DOP[7:0]. SBITERR/DBITERR outputs can also switch after
T1R if a single or double-bit error is detected on dataset A. Figure 4-32 shows a single-bit
error (SBITERR) being detected on data A in latch mode after clock edge T1R and a double-
bit error (DBITERR) being detected on data B in latch mode after clock edge T2R.
If attribute DO_REG is set to 1, DO[63:0] = A and DOP[7:0] = PA shortly after T2R.
Similarly, at time T3R and T4R, the memory content at address locations b and c are read
and decoded at DO[63:0] and DOP[7:0]. SBITERR/DBITERR outputs may also switch after
T2R if a single or double-bit error is detected on dataset A. Figure 4-32 shows a single-bit
error (SBITERR) being detected on data A in register mode after clock edge T2R and a
double-bit error (DBITERR) being detected on data B in register mode after clock edge T3R.
In ECC mode, the encode-only port and the decode-only port operate independently of
each other.
ECC Encode-Only
Set by Attributes
EN_ECC_READ = FALSE
EN_ECC_WRITE = TRUE
ECC Encode-Only Write
At time T1W, DI[63:0] = A is written into memory location a. The corresponding 8 bits of
ECC parity PA (hex) are generated internally, appended to the 64 data bits, and written into
the memory. Immediately after the write, the parity value PA appears at output
ECCPARITY[7:0]. Since ECC parity is generated internally, DIP[7:0] pins are not used.

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English