Xilinx virtex-5 fpga

196 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 5: Configurable Logic Blocks (CLBs)
Designing Large Multiplexers
4:1 Multiplexer
Each LUT can be configured into a 4:1 MUX. The 4:1 MUX can be implemented with a flip-
flop in the same slice. Up to four 4:1 MUXes can be implemented in a slice, as shown in
Figure 5-21.
X-Ref Target - Figure 5-21
Figure 5-21: Four 4:1 Multiplexers in a Slice
UG190_5_21_050506
(D[6:1])
(C[6:1])
(B[6:1])
(A[6:1])
(CLK)
CLK
6
SLICE
LUT
LUT
LUT
LUT
A[6:1]
O6
6
A[6:1]
O6
Registered
Output
4:1 MUX Output
(Optional)
DQ
(D)
(DQ)
Registered
Output
4:1 MUX Output
(Optional)
DQ
(C)
(CQ)
Registered
Output
4:1 MUX Output
(Optional)
DQ
(B)
(BQ)
Registered
Output
4:1 MUX Output
(Optional)
DQ
(A)
(AQ)
6
A[6:1]
O6
6
A[6:1]
O6
SEL D [1:0], DATA D [3:0]
Input
SEL C [1:0], DATA C [3:0]
Input
SEL B [1:0], DATA B [3:0]
Input
SEL A [1:0], DATA A [3:0]
Input