Xilinx virtex-5 fpga User Manual

362 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 8: Advanced SelectIO Logic Resources
Guidelines for Expanding the Serial-to-Parallel Converter Bit Width
1. Both ISERDES modules must be adjacent master and slave pairs. Both ISERDES
modules must be in NETWORKING mode because width expansion is not available in
MEMORY mode.
2. Set the SERDES_MODE attribute for the master ISERDES to MASTER and the slave
ISERDES to SLAVE. See “SERDES_MODE Attribute.”
3. The user must connect the SHIFTIN ports of the SLAVE to the SHIFTOUT ports of the
MASTER.
4. The SLAVE only uses the ports Q3 to Q6 as an input.
5. DATA_WIDTH applies to both MASTER and SLAVE in Figure 8-7.
X-Ref Target - Figure 8-7
Figure 8-7: Block Diagram of ISERDES Width Expansion
Q1D
Data Input
Q2
Q3
Q4
ISERDES
(Slave)
SERDES_MODE=SLAVE
Q5
Q6
Q1D
Q2
Q3
Q4
ISERDES
(Master)
SERDES_MODE=MASTER
Q5
Q6
SHIFTOUT1 SHIFTOUT2
SHIFTIN1 SHIFTIN2
Data_internal [0:5]
Data_internal [6:9]
ug190_8_07_100307

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English