Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA User Guide www.xilinx.com 111
UG190 (v5.0) June 19, 2009
PLL in Virtex-4 FPGA PMCD Legacy Mode
PLL in Virtex-4 FPGA PMCD Legacy Mode
Virtex-5 devices do not have Phase-Matched Clock Dividers (PMCDs). The Virtex-5 FPGA
PLL supports the Virtex-4 FPGA PMCD mode of operation. To take advantage of the
inherently more powerful features of the Virtex-5 FPGA PLL, Xilinx recommends
redesigning Virtex-4 FPGA PMCDs by implementing PLLs directly. The difference
between the Virtex-5 FPGA PLL and the Virtex-4 FPGA PMCD block in Virtex-4 FPGA
PMCD legacy mode is that only two clock inputs are supported in the Virtex-5 device
implementation. The Virtex-4 device implementation supported up to four clock inputs. If
four clock inputs must be used, then two PLLs can be put into PMCD mode. In this case,
delay matching is not optimal.
Figure 3-17 shows the Virtex-4 FPGA PMCD primitive implemented using a PLL. A PLL
can not be used as a PLL if it is already being used as a PMCD. To design-in the Virtex-5
FPGA PMCD functionality, instantiate a Virtex-4 FPGA PMCD primitive. ISE software
maps the Virtex-4 FPGA PMCD primitive into a Virtex-5 FPGA PLL.
Table 3-8 shows the port mapping between Virtex-5 FPGA PLL in PMCD legacy mode and
the Virtex-4 FPGA PMCD port names.
X-Ref Target - Figure 3-17
Figure 3-17: PMCD Primitive Implemented Using the PLL in PMCD Legacy Mode
Table 3-8: Mapping of Port Names
Virtex-4 FPGA
Port Name
Virtex-5 FPGA
Port Name
CLKA CLKIN
CLKB CLKFBIN
CLKC n/a
CLKD n/a
CLKA1 CLKOUT3
CLKA1D2 CLKOUT2
CLKA1D4 CLKOUT1
CLKA1D8 CLKOUT0
CLKFBOUT
CLKIN
CLKFBIN
O0
O1
O2
ug190_3_16_022207
O3
To B U F G

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English