Xilinx virtex-5 fpga User Manual

326 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 7: SelectIO Logic Resources
• Variable IDELAY (IDELAY_TYPE = VARIABLE) and fixed ODELAY mode
In this mode, only the IDELAY value can be dynamically changed after configuration
by manipulating the control signals CE and INC. The logic level of the T pin in the
IODELAY primitive dynamically determines if the block is in IDELAY or ODELAY
mode. When used in this mode, the IDELAYCTRL primitive must be instantiated. See
IDELAYCTRL Usage and Design Guidelines for more details.
Figure 7-6 lists the supported IODELAY configurations.
IODELAY Primitive
Figure 7-8 shows the IODELAY primitive.
Table 7-7 lists the available ports in the IODELAY primitive. All ports are 1-bit wide.
Table 7-6: IODELAY Configurations Supported
IODELAY
Mode
Direction of
IODELAY
Input Pin
Used in the
IODELAY
Element
Source Destination Supported Delay Modes
IDELAY
I IDATAIN IBUF
ILOGIC/ISERDES/Fabric Default/Fixed/Variable
DATAIN Fabric Fixed/Variable
ODELAY O ODATAIN
OLOGIC/OSERDES OBUF Fixed
Bidirectional
Delay
I (when T = 1) IDATAIN IBUF ILOGIC/ISERDES/Fabric Fixed/Variable
O (when T = 0) ODATAIN
OLOGIC/OSERDES OBUF Fixed
X-Ref Target - Figure 7-8
Figure 7-8: IODELAY Primitive
Table 7-7: IODELAY Primitive Ports
Port
Name
Direction Function
DATAOUT Output
Delayed data from one of three data input ports (IDATAIN,
ODATAIN, DATAIN)
IDATAIN Input Data input for IODELAY from the IOB.
ODATAIN Input Data input for IODELAY from the OSERDES/OLOGIC
ODATAIN DATAOUT
T
IDATAIN
CE
DATAIN
C
INC
RST
IODELAY
ug190_7_08_041106

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English