Xilinx virtex-5 fpga User Manual

286 www.xilinx.com Virtex-5 FPGA User Guide
UG190 (v5.0) June 19, 2009
Chapter 6: SelectIO Resources
Differential SSTL Class I (1.8V)
Figure 6-78 shows a sample circuit illustrating a valid termination technique for
differential SSTL Class I (1.8V) with unidirectional termination.
Figure 6-79 shows a sample circuit illustrating a valid termination technique for
differential SSTL Class I (1.8V) with unidirectional DCI termination.
X-Ref Target - Figure 6-78
Figure 6-78: Differential SSTL (1.8V) Class I Unidirectional Termination
X-Ref Target - Figure 6-79
Figure 6-79: Differential SSTL (1.8V) Class I Unidirectional DCI Termination
ug190_6_73_030506
+
–
External Termination
Z
0
IOB
IOB
DIFF_SSTL18_I
DIFF_SSTL18_I
Z
0
DIFF_SSTL18_I
V
TT
= 0.9V
50Ω
V
TT
= 0.9V
R
S
= 20Ω
R
P
= Z
0
= 50Ω
R
S
= 20Ω
ug190_6_74_032206
IOB
DIFF_SSTL18_I_DCI
DIFF_SSTL18_I_DCI
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
+
–
DCI
DIFF_SSTL18_I_DCI
V
CCO
= 1.8V
2R
VRP
= 2Z
0
= 100Ω
2R
VRN
= 2Z
0
= 100Ω
IOB
Z
0
Z
0
R
0
= 20Ω
R
0
= 20Ω

Xilinx virtex-5 fpga Specifications

General

Brand	Xilinx
Model	virtex-5 fpga
Category	Computer Hardware
Language	English